the ucd3138xa is a digital power supply controller from texas instruments offering superior levels of integration and performance in a single chip solution. the ucd3138128a offers 128 kb of program flash memory in comparison to 32 kb in ucd3138a. and it also provides additional options for communication such as spi and a second i2c/pmbus port. the availability of of program flash memory in multiple 32 kb banks enables designers to implement dual images of firmware (that is, one main image one back-up image) in the device and provides the option to execute from either of the banks using appropriate algorithms. it also creates the unique opportunity for the processor to load a new program and subsequently execute that program without interrupting power delivery. this feature allows the end user to add new features to the power supply in the field while eliminating any down-time required to load the new program.
the flexible nature of the ucd3138xa family makes it suitable for a wide variety of power conversion applications. in addition, multiple peripherals inside the device have been specifically optimized to enhance the performance of ac/dc and isolated dc/dc applications and reduce the solution component count in the it and network infrastructure space. the ucd3138xa family is a fully programmable solution offering customers complete control of their application, along with ample flexibility for many solutions. at the same time, ti is committed to simplifying our customer’s development effort through offering best in class development tools, including application firmware, code composer studiotm software development environment, and ti’s fusion power development gui which enables customers to configure and monitor key system parameters.
at the core of the controller are the digital power peripherals (dpp). each dpp implements a high speed digital control loop consisting of a dedicated error analog to digital converter (eadc), a pid based 2 pole - 2 zero digital compensator and dpwm outputs with 250 ps pulse width resolution. the device also contains a 12-bit, 539 ksps general purpose adc with up to 15 channels, timers, interrupt control, pmbus, i2c, spi and uart communications ports. the device is based on a 32-bit arm7tdmi-s risc microcontroller that performs real-time monitoring, configures peripherals and manages communications. the arm microcontroller executes its program out of programmable flash memory as well as on chip ram and rom.
in addition to the dpp, specific power management peripherals have been added to enable high efficiency across the entire operating range, high integration for increased power density, reliability, and lowest overall system cost and high flexibility with support for the widest number of control schemes and topologies. such peripherals include: light load burst mode, synchronous rectification, llc and phase shifted full bridge mode switching, input voltage feed forward, copper trace current sense, ideal diode emulation, constant current constant power control, synchronous rectification soft on and off, peak current mode control, flux balancing, secondary side input voltage sensing, high resolution current sharing, hardware configurable soft start with pre bias, as well as several other features. topology support has been optimized for voltage mode and peak current mode controlled phase shifted full bridge, single and dual phase pfc, bridgeless pfc, hard switched full bridge and half bridge, active clamp forward converter, two switch forward converter and llc half bridge and full bridge.
the ucd3138128a is a functional variant of the ucd3138 digital power controller that includes significant improvements over the ucd3138. for a description of the complete changes made in the ucd3138128a, refer to ucd3138128a migration guide. the major improvements are: the general purpose adc has been improved for better accuracy and performance at extreme cold temperatures (–40°c). the uart peripheral has been modified to include a hardware based auto-baud rate adjustment feature. a new synchronous rectifier dead time optimization hardware peripheral has been added. benefits include: improved efficiency reduced synchronous rectifier voltage stressesshorter development cyclea duty cycle read function has been added to improve use in peak current mode.
| 类型 | 标题 | 下载最新的英语版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | 数据表 | | | 2017年 1月 19日 | |||
| 应用手册 | | | | | 2024年 1月 2日 | |||
| 应用手册 | | | | | 2023年 9月 14日 | |||
| 应用手册 | | | | | 2023年 7月 5日 | |||
| 应用手册 | 2019年 6月 24日 | |||||
| 应用手册 | 2018年 11月 20日 | |||||
| 用户指南 | 2017年 9月 22日 |
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| 封装 | 引脚 | cad 符号、封装和 3d 模型 |
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| 80 |
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