和记娱乐手机app-和记娱乐ag旗舰版本下载 时钟和计时 时钟发生器
和记娱乐手机app-和记娱乐ag旗舰版本下载
时钟和计时
时钟发生器

cdce6214 数据表、产品信息和支持 | 德州仪器 ti.com.cn-和记娱乐手机app

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cdce6214

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function clock generator number of outputs 4 output frequency (max) (mhz) 350 core supply voltage (v) 1.8, 2.5, 3.3 output supply voltage (v) 1.8, 2.5, 3.3 input type lvcmos, universal input, xtal output type hcsl, lvcmos, lvds operating temperature range (°c) -40 to 105 features i2c, integrated eeprom, pin programmable, serial interface rating catalog
function clock generator number of outputs 4 output frequency (max) (mhz) 350 core supply voltage (v) 1.8, 2.5, 3.3 output supply voltage (v) 1.8, 2.5, 3.3 input type lvcmos, universal input, xtal output type hcsl, lvcmos, lvds operating temperature range (°c) -40 to 105 features i2c, integrated eeprom, pin programmable, serial interface rating catalog
24 16 mm² 4 x 4
  • configurable high performance, low-power, frac-n pll with rms jitter with spurs (12 khz – 20 mhz, fout > 100 mhz) as:
    • integer mode:
      • differential output: 350 fs typical, 600 fs maximum
      • lvcmos output: 1.05 ps typical, 1.5 ps maximum
    • fractional mode:
      • differential output: 1.7 ps typical, 2.1 ps maximum
      • lvcmos output: 2.0 ps typical, 4.0 ps maximum
  • supports pcie gen1/2/3/4 with ssc and gen 1/2/3/4/5 without ssc
  • 2.335-ghz to 2.625-ghz internal vco
  • typical power consumption: 65 ma for 4-output channel, 23 ma for 1-output channel.
  • universal clock input, two reference inputs for redundancy
    • differential ac-coupled or lvcmos: 10 mhz to 200 mhz
    • crystal: 10 mhz to 50 mhz
  • flexible output clock distribution
    • 4 channel dividers: up to 5 unique output frequencies from 24 khz to 328.125 mhz
    • combination of lvds-like, lp-hcsl or lvcmos outputs on out0 – out4 pins
    • glitchless output divider switching and output channel synchronization
    • individual output enable through gpio and register
  • frequency margining options
    • dco mode: frequency increment/decrement with 10ppb or less step-size
  • fully-integrated, configurable loop bandwidth: 100 khz to 1.6 mhz
  • single or mixed supply for level translation: 1.8 v/2.5 v/3.3 v
  • configurable gpios and flexible configuration options
    • i2c-compatible interface: up to 400 khz
    • integrated eeprom with two pages and external select pin. in-situ programming allowed.
  • supports 100-ω systems
  • low electromagnetic emissions
  • small footprint: 24-pin vqfn (4 mm × 4 mm)
  • configurable high performance, low-power, frac-n pll with rms jitter with spurs (12 khz – 20 mhz, fout > 100 mhz) as:
    • integer mode:
      • differential output: 350 fs typical, 600 fs maximum
      • lvcmos output: 1.05 ps typical, 1.5 ps maximum
    • fractional mode:
      • differential output: 1.7 ps typical, 2.1 ps maximum
      • lvcmos output: 2.0 ps typical, 4.0 ps maximum
  • supports pcie gen1/2/3/4 with ssc and gen 1/2/3/4/5 without ssc
  • 2.335-ghz to 2.625-ghz internal vco
  • typical power consumption: 65 ma for 4-output channel, 23 ma for 1-output channel.
  • universal clock input, two reference inputs for redundancy
    • differential ac-coupled or lvcmos: 10 mhz to 200 mhz
    • crystal: 10 mhz to 50 mhz
  • flexible output clock distribution
    • 4 channel dividers: up to 5 unique output frequencies from 24 khz to 328.125 mhz
    • combination of lvds-like, lp-hcsl or lvcmos outputs on out0 – out4 pins
    • glitchless output divider switching and output channel synchronization
    • individual output enable through gpio and register
  • frequency margining options
    • dco mode: frequency increment/decrement with 10ppb or less step-size
  • fully-integrated, configurable loop bandwidth: 100 khz to 1.6 mhz
  • single or mixed supply for level translation: 1.8 v/2.5 v/3.3 v
  • configurable gpios and flexible configuration options
    • i2c-compatible interface: up to 400 khz
    • integrated eeprom with two pages and external select pin. in-situ programming allowed.
  • supports 100-ω systems
  • low electromagnetic emissions
  • small footprint: 24-pin vqfn (4 mm × 4 mm)

the cdce6214 is a four-channel, ultra-low power, medium grade jitter, clock generator that can generate five independent clock outputs selectable between various modes of drivers. the input source could be a single-ended or differential input clock source, or a crystal. the cdce6214 features a frac-n pll to synthesize unrelated base frequency from any input frequency. the cdce6214 can be configured through the i2c interface. in the absence of the serial interface, the gpio pins can be used in pin mode to configure the product into distinctive configurations.

on-chip eeprom can be used to change the configuration, which is pre-selectable through the pins. the device provides frequency margining options with glitch-free operation to support system design verification tests (dvt) and ethernet audio-video bridging (eavb). fine frequency margining is available on any output channel by steering the fractional feedback divider in dco mode.

internal power conditioning provides excellent power supply ripple rejection (psrr), reducing the cost and complexity of the power delivery network. the analog and digital core blocks operate from either a 1.8-v, 2.5-v, or 3.3-v ±5% supply, and output blocks operate from a 1.8-v, 2.5-v, or 3.3-v ±5% supply.

the cdce6214 enables high-performance clock trees from a single reference at ultra-low power with a small footprint. the factory- and user-programmable eeprom features make the cdce6214 an easy-to-use, instant-on clocking device with a low power consumption.

the cdce6214 is a four-channel, ultra-low power, medium grade jitter, clock generator that can generate five independent clock outputs selectable between various modes of drivers. the input source could be a single-ended or differential input clock source, or a crystal. the cdce6214 features a frac-n pll to synthesize unrelated base frequency from any input frequency. the cdce6214 can be configured through the i2c interface. in the absence of the serial interface, the gpio pins can be used in pin mode to configure the product into distinctive configurations.

on-chip eeprom can be used to change the configuration, which is pre-selectable through the pins. the device provides frequency margining options with glitch-free operation to support system design verification tests (dvt) and ethernet audio-video bridging (eavb). fine frequency margining is available on any output channel by steering the fractional feedback divider in dco mode.

internal power conditioning provides excellent power supply ripple rejection (psrr), reducing the cost and complexity of the power delivery network. the analog and digital core blocks operate from either a 1.8-v, 2.5-v, or 3.3-v ±5% supply, and output blocks operate from a 1.8-v, 2.5-v, or 3.3-v ±5% supply.

the cdce6214 enables high-performance clock trees from a single reference at ultra-low power with a small footprint. the factory- and user-programmable eeprom features make the cdce6214 an easy-to-use, instant-on clocking device with a low power consumption.
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* 数据表 | 2020年 7月 2日
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— cdce6214-q1evm

the cdce6214-q1 evalution module (evm) is an evaluation platform for the cdce6214-q1 ultra-low power clock generator. this
evaluation module provides an usb-based interface to access the i2c bus to communicate with the cdce6214-q1. pin control mode can set the device in a specific operation
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